Section: New Results

Decoupled Graph-Coloring Register Allocation with Hierarchical Aliasing

Participants : Andre Tavares [UFMG, Brazil] , Quentin Colombet, Mariza Bigonha [UFMG, Brazil] , Christophe Guillon [stm icroelectronics] , Fernando Pereira [UFMG, Brazil] , Fabrice Rastello.

Decoupling spilling from register assignment, as mentioned in previous sections, has the main advantage of simplifying the implementation of register allocators. However, the decoupled model faces many problems when dealing with register aliasing, a phenomenon typical in architectures usually seen in embedded systems, such as ARM.

We introduced the semi-elementary form, a program representation that brings decoupled register allocation to architectures with register aliasing. The semi-elementary form is much smaller than program representations used by previous decoupled solutions, which leads to register allocators that perform better in terms of time and space. Furthermore, this representation reduces the number of copies that traditional allocators insert into assembly programs. We have empirically validated our results by showing that how our representation improves two well-known graph-coloring-based allocators, namely the iterated register coalescer (IRC) and Bouchez et al.'s brute force (BF) method, both augmented with Smith et al. extensions to handle aliasing. Running our techniques on SPEC CPU 2000, we have reduced the number of nodes in the interference graphs by a factor of 4 to 5, hence speeding-up the allocation time by a factor of 3 to 5. In addition, the semi-elementary form reduces by 8% the number of copies that IRC leaves uncoalesced.

This work is part of a collaboration with the Federal University of Minas Gerais. It has been presented at SCOPES'11 [13] .